A method of forming a metal interconnection line of a conventional semiconductor device will now be described with reference to FIGS. 1A to 1C.
Referring to FIG. 1A, a bottom glue layer 11 of Ti/TiN is formed on a semiconductor substrate 10 such as a silicon wafer by a sputtering method. Next, in a no vacuum-break condition, a metal layer 13 of Al—Cu or Al—Cl—Si is formed on the bottom glue layer 11 by a sputtering method. Next, a Ti/TiN layer is deposited on the metal layer 13 by a sputtering method to form a top anti-reflection coating (ARC) layer 15.
Referring to FIG. 1B, a photoresist layer pattern 17 is formed on the top ARC layer 15 by a photolithography process to expose portions of the top ARC layer 15.
Referring to FIG. 1C, the top ARC layer 15, the metal layer 13, and the bottom glue layer 11 are subsequently etched using the photoresist layer pattern 17 as a mask to form the metal interconnection lines 100. Each interconnection line is made of a top ARC pattern 15′, a metal pattern 13′, and a bottom glue pattern 11′. In FIG. 1C, reference number A indicates etched portions which electrically isolate the metal interconnection lines 100. Next, the photoresist layer pattern 17 is removed by a well-known method.
However, in the conventional method of forming the metal interconnection line described above, the metal layer 13 may be eroded when the metal layer 13 is etched and the photoresist layer pattern 17 is removed. In addition, the metal interconnection line may be destroyed due to electro-migration (EM) and stress-migration (SM).